View IDT71V124SA_156706.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
x x
IDT71V124SA
Features
128K x 8 advanced high-speed CMOS static RAM JEDEC revolutionary pinout (center power/GND) for reduced noise Equal access and cycle times - Commercial: 10/12/15/20ns - Industrial: 10/12/15/20ns One Chip Select plus one Output Enable pin Inputs and outputs are LVTTL-compatible Single 3.3V supply Low power consumption via chip deselect Available in a 32-pin 300- and 400-mil Plastic SOJ, and 32-pin Type II TSOP packages.
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The JEDEC center power/GND pinout reduces noise generation and improves system performance. The IDT71V124 has an output enable pin which operates as fast as 5ns, with address access times as fast as 9ns available. All bidirectional inputs and outputs of the IDT71V124 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.
x
x x x x x
Functional Block Diagram
A0
* * *
A16
ADDRESS DECODER
* * *
1,048,576-BIT MEMORY ARRAY
I/O0 - I/O7
8
8
I/O CONTROL
.
8
WE OE CS
CONTROL LOGIC
3873 drw 01
NOVEMBER 2003
1
(c)2003- Integrated Device Technology, Inc. DSC-3873/07
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Pin Configuration
A0 A1 A2 A3 CS I/O0 I/O1 VDD GND I/O2 I/O3 WE A4 A5 A6 A7 1 32 2 31 3 30 4 29 5 28 6 SO32-2 27 7 SO32-3 26 8 SO32-4 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 A16 A15 A14 A13 OE I/O7 I/O6 GND VDD I/O5 I/O4 A12 A11 A10 A9 A8
3873 drw 02
Absolute Maximum Ratings(1)
Symbol VDD VIN, VOUT Rating Supply Voltage Relative to GND Terminal Voltage Relative to GND Commercial Operating Temperature TA Industrial Operating Temperature -40 to +85 -55 to +125 -55 to +125 1.25 50
o
Value -0.5 to +4.6 -0.5 to VDD+0.5
Unit V V
-0 to +70
o
C
.
TBIAS TSTG PT IOUT
Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
C C
o
W mA
SOJ and TSOP Top View Truth Table(1)
CS L L L H OE L X H X WE H L H X I/O DATAOUT DATAIN High-Z High-Z Read Data Write Data Output Disabled Deselected - Standby
3873 tbl 01
3873 tbl 02 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty.
Function
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Temperature 0C to +70C -40C to +85C GND 0V 0V VDD See Below See Below
3873 tb l 02a
NOTE: 1. H = VIH, L = VIL, X = Don't care.
Recommended DC Operating Conditions
Symbol VDD(1) Parameter Supply Voltage Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.15 3.0 0 2.0 -0.5(1) Typ. 3.3 3.3 0
____ ____
Capacitance
(TA = +25C, f = 1.0MHz, SOJ package)
Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
3873 tbl 03
Max. 3.6 3.6 0 VDD+0.3 0.8
(3)
Unit V V V V V
3873 tbl 04
VDD(2) VSS VIH VIL
NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested.
DC Electrical Characteristics
Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage
NOTES: 1. For 71V124SA10 only. 2. For all speed grades except 71V124SA10. 3. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 4. VIL (min.) = -2V for pulse width less than 5ns, once per cycle.
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
Test Conditions VDD = Max., VIN = GND to VDD VDD = Max.,CS = VIH, VOUT = GND to VDD IOL = 8mA, VDD = Min. IOH = -4mA, VDD = Min. Min.
___ ___ ___
Max. 5 5 0.4
___
Unit A A V V
3873 tbl 05
2.4
2
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics(1, 2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD 0.2V)
71V124SA10 Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = fMAX(3) Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = fMAX(3) Full Standby Power Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(3) Com'l 145 45 10 Ind 150 50 10 71V124SA12 Com'l 130 40 10 Ind 140 40 10 71V124SA15 Com'l 100 35 10 Ind 120 40 10 71V124SA20 Com'l 95 30 10 Ind 115 35 10 Unit mA mA mA
3873 tbl 06
NOTES: 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD-0.2V (High). 3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figure 1 and 2
3873 tbl 07
3.3V 320 DATAOUT 5pF*
30pF
3873 drw 03
+1.5V 50 I/O Z0 = 50
350
3873 drw 04
.
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
3 6.42
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V124SA10 Symbol READ CYCLE tRC tAA tACS tCLZ(1) tCHZ tOE tOLZ
(1) (1)
71V124SA12 Min. Max.
71V124SA15 Min. Max.
71V124SA20 Min. Max. Unit
Parameter
Min.
Max.
Read Cycle Time Address Access Time Chip Select Access Time Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output Valid Output Enable to Output in Low-Z Output Disable to Output in High-Z Output Hold from Address Change
10
____
____
12
____
____
15
____
____
20
____
____
ns ns ns ns ns ns ns ns ns
10 10
____
12 12
____
15 15
____
20 20
____
____
____
____
____
4 0
____
4 0
____
4 0
____
4 0
____
5 5
____
6 6
____
7 7
____
8 8
____
0 0 4
0 0 4
0 0 4
0 0 4
tOHZ(1) tOH
5
____
5
____
5
____
7
____
WRITE CYCLE tWC tAW tCW tAS tWP tWR tDW tDH tOW(2) tWHZ
(2)
Write Cycle Time Address Valid to End-of-Write Chip Select to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Active from End-of-Write Write Enable to Output in High-Z
10 7 7 0 7 0 5 0 3 0
____
12 8 8 0 8 0 6 0 3 0
____
15 10 10 0 10 0 7 0 3 0
____
20 12 12 0 12 0 9 0 4 0
____
ns ns ns ns ns ns ns ns ns ns
3873 tbl 08
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
5
5
5
8
NOTES: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
4
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC ADDRESS tAA OE tOE CS tOLZ (5) tACS(3) tCLZ DATAOUT
(5)
tOHZ (5) tCHZ (5) DATAOUT VALID
3873 drw 05
HIGH IMPEDANCE
.
Timing Waveform of Read Cycle No. 2(1, 2, 4)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
3873 drw 06
.
NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state.
5 6.42
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC ADDRESS tAW CS tAS WE tWHZ (5) HIGH IMPEDANCE DATAOUT
(3) (3)
tWP (2)
tWR
tOW (5)
tCHZ (5)
tDW DATAIN DATAIN VALID
tDH
3873 drw 07
.
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC ADDRESS tAW CS tAS WE tDW DATAIN DATAIN VALID
3873 drw 08
tCW
tWR
(3)
tDH
.
NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW write period. 5. Transition is measured 200mV from steady state.
6
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Ordering Information
IDT 71V124 Device Type SA Power XX Speed X Package X Process/ Temperature Range Blank I TY Y PH 10 12 15 20 Commercial (0C to +70C) Industrial (-40C to +85C) 300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3) TSOP Type II (SO32-4)
Speed in nanoseconds
.
3873 drw 09
7 6.42
IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Center Power & Ground Pinout
Commercial and Industrial Temperature Ranges
Datasheet Document History
11/22/99 Pg. 1-4, 7 Pg. 2 Pg. 6 Pg. 8 Pg. 3 Pg. 4 Pg. 7 Pg. 1,3,7 Updated to new format Added Industrial Temperature range offerings Added Recommended Operating Temperature and Supply Voltage table Revised footnotes on Write Cycle No. 1 diagram Added Datasheet Document History Tighten ICC and ISB Tighten AC Characteristics tOHZ, tOW and tWHZ Removed footnote "400-mil SOJ package only offered in 10ns and 12ns speed grade" Added Industrial temperature offering 10ns speed grade
08/30/00 08/22/01 11/30/03
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
8
for Tech Support: sramhelp@idt.com 800-544-7726, x4033
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

▲Up To Search▲

Price & Availability of IDT71V124SA

	To Download IDT71V124SA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .